EDN

Tracking PLL design through the decades, part 2

The desire to integrate more gateshas driven two advances in CMOS-processingtechnology, enabling the integrationof practical inductors in genericCMOS-logic processes. The first, theuse of CMP ...
EDN

EDN — 11.23.95 straightforward techniques cut jitter in PLL-based clock driver

Jitter is extremely important in systems using PLL-based clock drivers. The effects of jitter range from none at all to complete system failure. This article describes jitter and its causes and ...