Historically, testability is an afterthought in the design process. But heightening complexity of chip designs, and especially SoCs, forces testability (and manufacturability) to take a more central ...

Design-for-test, or DFT, should facilitate high-quality test, not change the design. Test techniques and strategies need to supply a high-quality test that screens out defective devices, avoiding ...

An expert in finding solutions to IC nanometer design and manufacturing challenges, Joseph Sawicki is responsible for Mentor Graphics’ design-to-silicon products, including the Olympus-SoC ...

The testing and verification of semiconductor chips was a prominent topic at this year’s European Test Systems (ETS) conference, especially in the area of Design-for-Test (DFT) tools and techniques.

Until very recently, semiconductor design, verification, and test were separate domains. Those domains have since begun to merge, driven by rising demand for reliability, shorter market windows, and ...

In today’s highly competitive semiconductor industry, chip-design companies strive for competitive advantages by optimizing designs for PPA (Power, Performance, Area). Along with the functional logic, ...

Siemens has acquired Aster Technologies, a privately held company in the printed circuit board market. Aster produces test verification and engineering software. This strategic move integrates Aster’s ...

Connected devices and systems have become an integral part of our everyday life and we take this for granted. Finding the fastest way to our destination with a smartphone, reading the news on a tablet ...

Join us on Wednesday, December 15 at noon Pacific for the Design for Test Hack Chat with Duncan Lowder! If your project is at the breadboard phase, or even if you’ve moved to a PCB prototype, it’s ...