The semiconductor industry has long relied on scan ATPG (automatic test pattern generation) tools instead of functional test to create stimulus-response patterns with very high fault coverage. But ...

Low-power design and fast testing at the fab are not happy bedfellows. As Giri Podichetty of Mentor Graphics explains at Semiwiki and in a white paper, “the goal of automatic test pattern generation ...

The trend in semiconductors leads to more IC test data volume, longer test times, and higher test costs. Embedded deterministic test (EDT) has continued to deliver more compression, which has been ...

For testing complex chip designs it makes sense to combine the two most common test methodologies -logic built-in self-test (LBIST) and automatic test pattern generation (ATPG), writes Amer ...

Patterns created using advanced fault models provide higher test coverage, improved defect detection, and higher-yielding ...

Automatic test-pattern generation (ATPG) has played a key role in semiconductor logic test, but several trends driving the need for semiconductor test quality are challenging traditional ATPG tools.

There is a rapidly growing interest in the use of structural techniques for testing random logic. In particular, much has been published on new techniques for on-chip compression of automatic test ...

Design for test (DFT) has been around since the 1960s. The technology was developed to reduce the cost of creating a successful test for an IC. Scan design, fault models, and automatic test pattern ...

Advanced ATPG products support simultaneous analysis of multiple fault models, leverage multi-threading and on-chip compression to improve quality and reduce turnaround time and costs of nanometer ICs ...